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1/15 december 2004 this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. vn750pep-e high side driver rev. 3 table 1. general features cmos compatible input on state open load detection off state open load detection shorted load protection undervoltage and overvoltage shutdown protection against loss of ground very low stand-by current reverse battery protection (*) in compliance with the 2002/95/ec european directive description the vn750pep-e is a monolithic device designed in stmicroelectronics vipower m0-3 technology, intended for driving any kind of load with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). figure 1. package active current limitation combined with thermal shutdown and automatic restart protect the device against overload. the device detects open load condition both is on and off state. output shorted to v cc is detected in the off state. device automatically turns off in case of ground pin disconnection. table 2. order codes note: (*) see application schematic at page 9. typ e r ds(on) i out v cc vn750pep-e 60 m ? 6 a 36 v powersso-12 package tube tape and reel powersso-12 vn750pep-e VN750PEPTR-E preliminary data
vn750pep-e 2/15 figure 2. block diagram table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage -0.3 v - i gnd dc reverse ground pin current -200 ma i out dc output current internally limited a - i out reverse dc output current -6 a i in dc input current +/- 10 ma i stat dc status current +/- 10 ma v esd electrostatic discharge (human body model: r=1.5k ?; c=100pf) - input - status - output - v cc 4000 4000 5000 5000 v v v v p tot power dissipation t c =25c 74 w t j junction operating temperature internally limited c t c case operating temperature - 40 to 150 c t stg storage temperature - 55 to 150 c undervoltage overtemperature v cc gnd input output overvoltage current limiter logic driver power clamp status v cc clamp on state openload off state openload and output shorted to v cc detection detection detection detection detection
3/15 vn750pep-e figure 3. configuration diagram (top view) & suggested connections for unused and n.c. pins figure 4. current and voltage conventions table 4. thermal data note: 1. when mounted on a standard single-sided fr-4 board with 1cm 2 of cu (at least 35 m thick) connected to all v cc pins. note: 2. when mounted on a standard single-sided fr-4 board with 8cm 2 of cu (at least 35 m thick) connected to all v cc pins. symbol parameter value unit r thj-case thermal resistance junction-case max 1.7 c/w r thj-amb thermal resistance junction-ambient max 61 (1) 50 (2) c/w connection / pin status n.c. output input floating x x x x to ground x through 10k ? resistor 1 2 3 4 5 6 output output output output status v cc gnd v cc 12 11 10 9 8 7 input n.c. output output tab = v cc input i s i in v in v cc status i stat v stat gnd v cc i out v out i gnd output v f
vn750pep-e 4/15 electrical characteristics (8v8v i out =2a; v cc >8v 60 120 m ? m ? i s supply current off state; v cc =13v; v in =v out =0v off state; v cc =13v; v in =v out =0v; t j =25 c on state; v cc =13v; v in =5v; i out =0a 10 10 2 25 20 3.5 a a ma i l(off1) off state output current v in =v out =0v 0 50 a i l(off2) off state output current v in =0v; v out =3.5v -75 0 a i l(off3) off state output current v in =v out =0v; v cc =13v; t j =125c 5 a i l(off4) off state output current v in =v out =0v; v cc =13v; t j =25c 3 a symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time r l =6.5 ? from v in rising edge to v out =1.3v 40 s t d(off) turn-off delay time r l =6.5 ? from v in falling edge to v out =11.7v 30 s dv out / dt (on) turn-on voltage slope r l =6.5 ? from v out =1.3v to v out =10.4v 0.5 v/ s dv out / dt (off) turn-off voltage slope r l =6.5 ? from v out =11.7v to v out =1.3v 0.2 v/ s symbol parameter test conditions min. typ. max. unit v il input low level 1.25 v i il low level input current v in =1.25v 1 a v ih input high level 3.25 v i ih high level input current v in =3.25v 10 a v hyst input hysteresis voltage 0.5 v v icl input clamp voltage i in =1ma i in =-1ma 66.8 -0.7 8v v
5/15 vn750pep-e electrical characteristics (continued) table 8. v cc - output diode table 9. status pin table 10. protections (see note 1) note: 1. to ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic sign als must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. table 11. openload detection symbol parameter test conditions min. typ. max. unit v f forward on voltage -i out =1.3a; t j =150c 0.6 v symbol parameter test conditions min typ max unit v stat status low output voltage i stat =1.6ma 0.5 v i lstat status leakage current normal operation; v stat =5v 10 a c stat status pin input capacitance normal operation; v stat =5v 100 pf v scl status clamp voltage i stat =1ma i stat =-1ma 66.8 -0.7 8v v symbol parameter test conditions min typ max unit t tsd shut-down temperature 150 175 200 c t r reset temperature 135 c t hyst thermal hysteresis 7 15 c t sdl status delay in overload condition t j >t jsh 20 s i lim current limitation 9v vn750pep-e 6/15 figure 5. table 12. truth table figure 6. switching time waveforms conditions input output status normal operation l h l h h h current limitation l h h l x x h (t j < t tsd ) h (t j > t tsd ) l overtemperature l h l l h l undervoltage l h l l x x overvoltage l h l l h h output voltage > v ol l h h h l h output current < i ol l h l h h l v in v stat t dol(off) open load status timing (with external pull-up) overtemp status timing i out < i ol v out > v ol t dol(on) t j > t jsh v in v stat t sdl t sdl t t v out v in 80% 10% dv out /dt (on) t d(off) 90% dv out /dt (off) t d(on)
7/15 vn750pep-e table 13. electrical transient requirements on v cc pin iso t/r 7637/1 test pulse test levels i ii iii iv delays and impedance 1 -25 v -50 v -75 v -100 v 2 ms 10 ? 2 +25 v +50 v +75 v +100 v 0.2 ms 10 ? 3a -25 v -50 v -100 v -150 v 0.1 s 50 ? 3b +25 v +50 v +75 v +100 v 0.1 s 50 ? 4 -4 v -5 v -6 v -7 v 100 ms, 0.01 ? 5 +26.5 v +46.5 v +66.5 v +86.5 v 400 ms, 2 ? iso t/r 7637/1 test pulse test levels results i ii iii iv 1cccc 2cccc 3acccc 3bcccc 4cccc 5c e e e class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
vn750pep-e 8/15 figure 7. waveforms open load without external pull-up status input normal operation undervoltage v cc v usd v usdhyst input overvoltage v cc v cc >v ov status input status status input status input open load with external pull-up undefined load voltage v cc v ol v ol
9/15 vn750pep-e figure 8. application schematic gnd protection network against reverse battery solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1) r gnd 600mv / (i s(on)max ). 2) r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device?s datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsd. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not common with the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the st suggests to utilize solution 2 (see below). solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k ?) should be inserted in parallel to d gnd if the device will be driving an inductive load. this small signal diode can be safely shared amongst several different hsd. also in this case, the presence of the ground network will produce a shift ( j 600mv) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. series resistor in input and status lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. safest configuration for unused input and status pin is to leave them unconnected. load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds v cc max dc rating. the same applies if the device will be subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. c i/os protection: if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup 20ma; v oh c 4.5v 5k ? r prot 65k ? . recommended r prot value is 10k ?. v cc gnd output d gnd r gnd d ld c +5v r prot v gnd status input +5v r prot
vn750pep-e 10/15 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l 11/15 vn750pep-e powersso-12 thermal data figure 10. powersso-12 pc board figure 11. r thj-amb vs pcb copper area in open box free air condition layout condition of r th and z th measurements (pcb fr4 area= 78mm x 78mm, pcb thickness=2mm, cu thickness=35 m, copper areas: from minimum pad lay-out to 8cm 2 ). 45 50 55 60 65 70 0246810 rthj_amb(c/w) pcb cu heatsink area (cm^2)
vn750pep-e 12/15 figure 12. powersso-12 thermal impedance junction ambient single pulse figure 13. thermal fitting model of a single channel hsd in powersso-12 pulse calculation formula table 14. thermal parameter 0.01 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/ w) footprint 8 cm 2 area/island (cm 2 ) footprint 8 r1 (c/w) 0.1 r2 (c/w) 0.6 r3 (c/w) 1.5 r4 (c/w) 8 r5 (c/w) 28 18 r6 (c/w) 30 22 c1 (w.s/c) 0.001 c2 (w.s/c) 0.0035 c3 (w.s/c) 0.015 c4 (w.s/c) 0.1 c5 (w.s/c) 0.15 0.017 c6 (w.s/c) 3 5 z th r th z thtp 1 ? () + = where t p t ? =
13/15 vn750pep-e package mechanical table 15. powersso-12? mechanical data figure 14. powersso-12? package dimensions symbol millimeters min typ max a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0o 8o x 1.900 2.500 y 3.600 4.200 ddd 0.100
vn750pep-e 14/15 revision history table 16. revision history date revision description of changes oct. 2004 1 - first issue. nov. 2004 2 - powersso-12 thermal charact. insertion. dec. 2004 3 - thermal data correction.
15/15 vn750pep-e i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express written approval of stmicroelectron ics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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